Details


8 Building Blocks of Integrated- Circuit Amplifiers 
Introduction 
8.1 IC Design Philosophy 
8.2 IC Biasing—Current Sources,
Current Mirrors, and Current-Steering
Circuits 
8.2.1 The Basic MOSFET Current
Source 
8.2.2 MOS Current-Steering
Circuits 
8.2.3 BJT Circuits 
8.2.4 Small-Signal Operation of Current
Mirrors 
8.3 The Basic Gain Cell 
8.3.1 The CS and CE Amplifiers with
Current-Source Loads 
8.3.2 The Intrinsic Gain 
8.3.3 Effect of the Output Resistance of the
Current-Source Load 
8.3.4 Increasing the Gain of the Basic
Cell
8.4 The Common-Gate and Common-Base
Amplifier
8.4.1 The CG Circuit
8.4.2 Output Resistance of a CS Amplifier
with a Source Resistance 
8.4.3 The Body Effect 
8.4.4 The CB Circuit 
8.4.5 Output Resistance of an Emitter-
Degenerated CE Amplifier 
8.5 The Cascode Amplifier 
8.5.1 Cascoding 
8.5.2 The MOS Cascode Amplifier 
8.5.3 Distribution of Voltage Gain in a
Cascode Amplifier
8.5.4 Double Cascoding 
8.5.5 The Folded Cascode 
8.5.6 The BJT Cascode 
8.6 Current-Mirror Circuits with Improved
Performance 
8.6.1 Cascode MOS Mirrors 
8.6.2 The Wilson Current Mirror 
8.6.3 The Wilson MOS Mirror 
8.6.4 The Widlar Current Souce 
8.7 Some Useful Transistor Pairings 
8.7.1 The CC–CE, CD–CS, and CD–CE
Configurations 
8.7.2 The Darlington Configuration 
8.7.3 The CC–CB and CD–CG
Configurations 

9 Differential and Multistage Amplifiers 
Introduction 
9.1 The MOS Differential Pair
9.1.1 Operation with a Common-Mode
Input Voltage 
9.1.2 Operation with a Differential Input
Voltage 
9.1.3 Large-Signal Operation 
9.1.4 Small-Signal Operation 
9.1.5 The Differential Amplifier with
Current-Source Loads 
9.1.6 Cascode Differential
Amplifier 
9.2 The BJT Differential Pair 
9.2.1 Basic Operation 
9.2.2 Input Common-Mode Range 
9.2.3 Large-Signal Operation 
9.2.4 Small-Signal Operation 
9.3 Common-Mode Rejection 
9.3.1 The MOS Case 
9.3.2 The BJT Case 
9.4 DC Offset
9.4.1 Input Offset Voltage of the MOS
Differential Amplifier  
9.4.2 Input Offset Voltage of the Bipolar
Differential Amplifier
9.4.3 Input Bias and Offset Currents of the
Bipolar Differential Amplifier 
9.4.4 A Concluding Remark 
9.5 The Differential Amplifier with a
Current-Mirror Load 
9.5.1 Differential to Single-Ended
Conversion 
9.5.2 The Current-Mirror-Loaded MOS
Differential Pair 
9.5.3 Differential Gain of the
Current-Mirror-Loaded MOS
Pair 
9.5.4 The Bipolar Differential Pair with a
Current-Mirror Load 
9.5.5 Common-Mode Gain and
CMRR 
9.6 Multistage Amplifiers 
9.6.1 A Two-Stage CMOS
Op Amp 659
9.6.2 A Bipolar Op Amp 
 
10 Frequency Response
Introduction 
10.1 Low-Frequency Response of
Discrete-Circuit Common-
Source and Common-Emitter
Amplifiers 
10.1.1 The CS Amplifier 
10.1.2 The Method of Short-Circuit
Time-Constants 
10.1.3 The CE Amplifier 
10.2 Internal Capacitive Effects and the
High-Frequency Model of the MOSFET
and the BJT
10.2.1 The MOSFET 
10.2.2 The BJT
10.3 High-Frequency Response of the CS
and CE Amplifiers 
10.3.1 The Common-Source
Amplifier 
10.3.2 The Common-Emitter
Amplifier 
10.3.3 Miller’s Theorem 
10.3.4 Frequency Response of the CS
Amplifier When Rsig Is Low 
10.4 Useful Tools for the Analysis of
the High-Frequency Response of
Amplifiers 
10.4.1 The High-Frequency Gain
Function 
10.4.2 Determining the 3-dB
Frequency fH 
10.4.3 The Method of Open-Circuit
Time Constants 
10.4.4 Application of the Method of
Open-Circuit Time Constants to
the CS Amplifier 
10.4.5 Application of the Method of
Open-Circuit Time Constants to
the CE Amplifier 
10.5 High-Frequency Response of
the Common-Gate and Cascode
Amplifiers 
10.5.1 High-Frequency Response of the
CG Amplifier 
10.5.2 High-Frequency Response of the
MOS Cascode Amplifier 
10.5.3 High-Frequency Response of the
Bipolar Cascode Amplifier 
10.6 High-Frequency Response of the
Source and Emitter Followers 
10.6.1 The Source-Follower Case 
10.6.2 The Emitter-Follower Case 
10.7 High-Frequency Response of
Differential Amplifiers 
10.7.1 Analysis of the Resistively Loaded
MOS Amplifier 
10.7.2 Analysis of the Current-Mirror-
Loaded MOS Amplifier 
10.8 Other Wideband Amplifier
Configurations 
10.8.1 Obtaining Wideband
Amplification by Source and
Emitter Degeneration
10.8.2 The CD–CS, CC–CE, and
CD–CE Configurations 
10.8.3 The CC–CB and CD–CG
Configurations 

11 Feedback 
Introduction 
11.1 The General Feedback Structure 
11.1.1 Signal-Flow Diagram 
11.1.2 The Closed-Loop Gain 
11.1.3 The Loop Gain 
11.1.4 Summary 
11.2 Some Properties of Negative
Feedback 
11.2.1 Gain Desensitivity 
11.2.2 Bandwidth Extension 
11.2.3 Interference Reduction 
11.2.4 Reduction in Nonlinear
Distortion 
11.3 The Feedback Voltage Amplifier 
11.3.1 The Series–Shunt Feedback
Topology 
11.3.2 Examples of Series–Shunt
Feedback Amplifiers 
11.3.3 Analysis of the Feedback Voltage
Amplifier Utilizing the Loop
Gain 
11.3.4 A Final Remark 
11.4 Systematic Analysis of Feedback
Voltage Amplifiers 
11.4.1 The Ideal Case 
11.4.2 The Practical Case 
11.5 Other Feedback Amplifier Types 
11.5.1 Basic Principles 
11.5.2 The Feedback Transconductance
Amplifier (Series–Series) 
11.5.3 The Feedback Transresistance
Amplifier (Shunt–Shunt) 
11.5.4 The Feedback Current Amplifier
(Shunt–Series) 
11.6 Summary of the Feedback Analysis
Method 
11.7 The Stability Problem 
11.7.1 Transfer Function of the Feedback
Amplifier 
11.7.2 The Nyquist Plot 
11.8 Effect of Feedback on the Amplifier
Poles 
11.8.1 Stability and Pole Location 
11.8.2 Poles of the Feedback
Amplifier 
11.8.3 Amplifier with a Single-Pole
Response 
11.8.4 Amplifier with a Two-Pole
Response 
11.8.5 Amplifiers with Three or More
Poles 
11.9 Stability Study Using Bode Plots 
11.9.1 Gain and Phase Margins 
11.9.2 Effect of Phase Margin on
Closed-Loop Response 
11.9.3 An Alternative Approach for
Investigating Stability 
11.10 Frequency Compensation 
11.10.1 Theory 
11.10.2 Implementation
11.10.3 Miller Compensation and Pole
Splitting 

12 Output Stages and Power Amplifiers 
Introduction 
12.1 Classification of Output Stages 
12.2 Class A Output Stage 
12.2.1 Transfer Characteristic 
12.2.2 Signal Waveforms 
12.2.3 Power Dissipation 
12.2.4 Power-Conversion
Efficiency 
12.3 Class B Output Stage 
12.3.1 Circuit Operation 
12.3.2 Transfer Characteristic 
12.3.3 Power-Conversion Efficiency 
12.3.4 Power Dissipation 
12.3.5 Reducing Crossover
Distortion 
12.3.6 Single-Supply Operation 
12.4 Class AB Output Stage 
12.4.1 Circuit Operation 
12.4.2 Output Resistance 
12.5 Biasing the Class AB Circuit 
12.5.1 Biasing Using Diodes 
12.5.2 Biasing Using the VBE
Multiplier 
12.6 Variations on the Class AB
Configuration 
12.6.1 Use of Input Emitter
Followers 
12.6.2 Use of Compound Devices 
12.6.3 Short-Circuit Protection 
12.6.4 Thermal Shutdown 
12.7 CMOS Class AB Output Stages 
12.7.1 The Classical Configuration 
12.7.2 An Alternative Circuit
Utilizing Common-Source
Transistors 
12.8 IC Power Amplifiers 
12.8.1 A Fixed-Gain IC Power
Amplifier 
12.8.2 The Bridge Amplifier 
12.9 Class D Power Amplifiers 
12.10 Power Transistors 
12.10.1 Packages and Heat
Sinks 
12.10.2 Power BJTs 
12.10.3 Power MOSFETs 
12.10.4 Thermal Considerations 

13 Operational-Amplifier Circuits 
Introduction 
13.1 The Two-Stage CMOS Op Amp 
13.1.1 The Circuit 
13.1.2 Input Common-Mode Range and
Output Swing 
13.1.3 DC Voltage Gain 
13.1.4 Common-Mode Rejection Ratio
(CMRR) 
13.1.5 Frequency Response 
13.1.6 Slew Rate 
13.1.7 Power-Supply Rejection Ratio
(PSRR) 
13.1.8 Design Trade-Offs 
13.1.9 A Bias Circuit for the Two-Stage
CMOS Op Amp 
13.2 The Folded-Cascode CMOS Op
Amp 
13.2.1 The Circuit 
13.2.2 Input Common-Mode Range and
Output Swing 
13.2.3 Voltage Gain 
13.2.4 Frequency Response 
13.2.5 Slew Rate 
13.2.6 Increasing the Input Common-
Mode Range: Rail-to-Rail Input
Operation 
13.2.7 Increasing the Output Voltage
Range: The Wide-Swing Current
Mirror 
13.3 The 741 BJT Op Amp 
13.3.1 The 741 Circuit 
13.3.2 DC Analysis 
13.3.3 Small-Signal Analysis 
13.3.4 Frequency Response 
13.3.5 Slew Rate 
13.4 Modern Techniques for the Design of
BJT Op Amps 
13.4.1 Special Performance
Requirements 
13.4.2 Bias Design 
13.4.3 Design of the Input Stage to
Obtain Rail-to-Rail VICM 
13.4.4 Common-Mode Feedback to
Control the DC Voltage at the
Output of the Input Stage 
13.4.5 Output-Stage Design for Near
Rail-to-Rail Output Swing 1
13.4.6 Concluding Remark